EP1K10TC100-2N vs EP1K10TC100-3 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1K10TC100-2N sa pamamagitan ng Altera at EP1K10TC100-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP1K10TC100-2N EP1K10TC100-2N - ACEX-1K FPGA, 10K Gates, 576 Cells | Altera

EP1K10TC100-2N - ACEX-1K FPGA, 10K Gates, 576 Cells | Altera

EP1K10TC100-2N ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP1K10TC100-2N EP1K10TC100-3
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family ACEX-1K ACEX-1K
Logic Elements / Cells 576 —
Typical Gates 10,000 10,000
Logic Array Blocks (LABs) 72 —
Embedded Memory (EAB) 12,288 bits —
Maximum User I/O 66 —
Process Technology 0.22 um CMOS 0.22 µm CMOS
Core Voltage (VCCINT) 2.5 V —
I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5 V —
Speed Grade -2 -3 (fastest commercial)
Maximum Frequency 200 MHz —
Packhaging 100-pin TQFP (1.0 mm body, 0.5 mm pitch) 100-pin TQFP (TQFP-100)
Temperature na Operasyon 0 C to +70 C (commercial) [DATA_NEEDED: operating temperature grade]
Configuration Modes Passive Serial, Active Serial, JTAG —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS Lead-free / RoHS compliant [DATA_NEEDED: RoHS status]
Number of Logic Elements (LEs) — 576
Number of LABs — 72
Number of EABs — 3
Total RAM Bits — 12,288
User I/O Pins — 66
Operating Frequency (max) — 200 MHz
Core Voltage — 2.5 V
Programming Interface — JTAG (IEEE 1149.1)
Supported I/O Standards — LVTTL, LVCMOS, PCI
Memory Configuration — Dual-port RAM supported (per family)

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