EP1K50QC208-2N vs EP1K50QC208-3N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1K50QC208-2N sa pamamagitan ng Intel at EP1K50QC208-3N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1K50QC208-2N EP1K50QC208-3N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series ACEX-1K —
Family ACEX 1K ACEX-1K
Logic Elements 2,880 —
Typical Gates 50,000 50,000
Logic Array Blocks (LABs) 360 360
Embedded Memory (EAB SRAM) 40 kbit —
User I/Os 147 —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Maximum Toggle Frequency 200 MHz —
Pin-to-Pin Delay (LE) 0.4 ns (per data sheet snippet) —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Supply Voltage 2.5 V —
I/O Supply Voltage [DATA_NEEDED: I/O supply voltage] —
Configuration Interface JTAG (IEEE 1149.1), Serial (PS/AS) —
Packhaging 208-pin PQFP (BFQFP) 208-pin PQFP / BFQFP (Plastic Quad Flat Pack)
Uri ng Pagpapasok Surface Mount (Gull-Wing) Surface Mount
Temperature na Operasyon 0 °C to 85 °C (Commercial) 0 °C to +70 °C (Commercial)
Level ng MSL [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: RoHS status] —
Logic Elements (LEs) — 2,880
Embedded RAM — 40,960 bits (10 EABs × 4,096 bits)
Maximum User I/Os — 147
Maximum Operating Frequency — 166.67 MHz
Pin-to-Pin Logic Delay — 0.5 ns (typical, -3 speed grade)
Core Supply Voltage (VCCINT) — 2.5 V
I/O Supply Voltage (VCCIO) — 3.3 V (PCI-compatible I/O banks)
Programming Interface — IEEE 1149.1 JTAG + in-system configurable
Lead-Free / RoHS — Compliant (Pb-free terminal finish per 'N' suffix)

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