EP1K50QI208-2 vs EP1K50QC208-2N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1K50QI208-2 sa pamamagitan ng Altera at EP1K50QC208-2N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1K50QI208-2 EP1K50QC208-2N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series ACEX 1K ACEX-1K
Manufacturer Altera (Intel) —
Typical Gate Count 50,000 gates —
Logic Elements (LEs) 2,880 —
Logic Array Blocks (LABs) 360 360
Embedded SRAM 40,960 bits —
Maximum User I/O Pins 147 —
Speed Grade -2 —
Core Voltage 2.5 V —
I/O Voltage Support 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
Package Type 208-pin PQFP (Power Quad Flat Pack) —
Uri ng Pagpapasok Surface Mount Surface Mount (Gull-Wing)
Process Technology CMOS, SRAM-based configuration 0.22 µm CMOS
Configuration Method JTAG / serial configuration PROM (EPC2/EPCS) —
Temperature na Operasyon -40C to +85C (industrial) 0 °C to 85 °C (Commercial)
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Family — ACEX 1K
Logic Elements — 2,880
Typical Gates — 50,000
Embedded Memory (EAB SRAM) — 40 kbit
User I/Os — 147
Number of I/O Banks — [DATA_NEEDED: number of I/O banks]
Maximum Toggle Frequency — 200 MHz
Pin-to-Pin Delay (LE) — 0.4 ns (per data sheet snippet)
Core Supply Voltage — 2.5 V
I/O Supply Voltage — [DATA_NEEDED: I/O supply voltage]
Configuration Interface — JTAG (IEEE 1149.1), Serial (PS/AS)
Packhaging — 208-pin PQFP (BFQFP)
Level ng MSL — [DATA_NEEDED: MSL level]

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