EP1M120F484-I6 vs EP1M120F484C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1M120F484-I6 sa pamamagitan ng Altera at EP1M120F484C6 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1M120F484-I6 | EP1M120F484C6 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Mercury FPGA | Mercury (APEX EP1M) |
| Logic Elements (LEs) | 4,800 | 49,152 (per distributor listing) |
| Equivalent Gates | 120,000 | — |
| Logic Array Blocks (LABs) | 480 | 480 |
| User I/Os | 303 | — |
| High-Speed Transceivers | Up to 12 channels | — |
| Transceiver Data Rate | Up to 1.25 Gbps per channel | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.18 µm CMOS | [DATA_NEEDED: process node] |
| Packhaging | 484-pin FBGA (FineLine BGA) | 484-ball FC-FBGA (FineLine BGA) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | -40 °C to +100 °C (industrial) | 0 C to +85 C (Commercial) |
| Speed Grade | -6 | — |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, JTAG, EPC device | — |
| I/O Standards | LVTTL, LVCMOS, PCI, LVDS, LVPECL, HSTL | — |
| Typical Gates | — | 120,000 |
| Logic Cells | — | 4,800 |
| User I/O | — | 303 |
| Ball Pitch | — | [DATA_NEEDED: ball pitch] |
| Core Supply Voltage | — | 1.8 V |
| Logic Family | — | CMOS |
| Integrated Transceivers | — | High-speed CDR to 1.25 Gbps |
| Embedded System Blocks (ESBs) | — | Yes (dual-port RAM / ROM / CAM) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |