EP1S10F672C6 vs EP1S10B672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F672C6 sa pamamagitan ng Intel at EP1S10B672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S10F672C6 | EP1S10B672C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Series | Stratix® I | Stratix |
| Family | Stratix FPGA | — |
| Logic Elements (LE) | 10,570 | — |
| Logic Array Blocks (LABs) | 1057 | — |
| Total Memory Bits | 920,448 bits | — |
| Embedded Memory | TriMatrix (MRAM/M4K) | — |
| DSP Blocks | 6 | Yes (DSP multiplier blocks) |
| Number of I/Os | 345 | — |
| Number of PLLs | 12 (6 per device side) | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Packhaging | 672-ball FineLine BGA (FBGA) | — |
| Temperature na Operasyon | 0C to +85C (Commercial) | 0 °C to 85 °C (Commercial) |
| Maximum Core Frequency | 420.17 MHz | — |
| Configuration Modes | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements | — | 10,570 |
| Embedded Memory (Total) | — | 920 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| Supply Voltage (Core) | — | 1.5 V |
| Package Type | — | 672-ball FineLine BGA |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.27 mm |
| Logic Family | — | CMOS |
| Temperature Grade | — | Commercial (C) |
| Speed Grade | — | 7 |
| Configuration Method | — | JTAG / EPC serial configuration |