EP1S10F672C7 vs EP1S10F672I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F672C7 sa pamamagitan ng Altera at EP1S10F672I7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S10F672C7 | EP1S10F672I7 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | Stratix | Stratix |
| Logic Elements | 10,570 | 10,570 |
| Embedded Memory | 920,448 bits | — |
| User I/Os | 345 | — |
| Packhaging | 672-pin FBGA (FineLine BGA) | FBGA-672, 35 x 35 mm, 1.27 mm pitch |
| Package Dimensions | 35 x 35 mm, 1.27 mm pitch | — |
| Process Technology | 130 nm CMOS | 0.13 um CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| Logic Cells | 10,570 | — |
| LABs (Logic Array Blocks) | 1,057 | — |
| Temperature na Operasyon | 0 C to 85 C (Commercial) | 0 C to +85 C (industrial grade, I7) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| I/O Standards | LVTTL, LVCMOS, LVDS, SSTL, HSTL | — |
| Configuration Mode | JTAG, Passive Serial, Active Serial | — |
| Tindminan RoHS | unknown | unknown - verify per lot |
| User I/O Pins | — | 345 |
| Core Supply Voltage | — | 1.5 V |
| Maximum Internal Clock | — | 420.17 MHz (per datasheet) |
| Logic Family | — | CMOS |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Total Pins | — | 672 (FBGA) |
| Configuration Method | — | JTAG / serial / parallel PROM |
| Uri ng Memory | — | TriMatrix embedded block RAM + distributed RAM |
| DSP Blocks | — | Yes (dedicated hardware multipliers) |