EP1S10F780C5N vs EP1S10F780C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F780C5N sa pamamagitan ng Intel at EP1S10F780C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S10F780C5N - Stratix 10570 Cells FPGA, 780-FBGA | Intel (Altera)
EP1S10F780C5N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1S10F780C5N | EP1S10F780C6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix | Stratix |
| Logic Elements | 10570 | — |
| Total RAM Bits | 920448 | — |
| User I/O Count | 426 | 426 (per FindIC) |
| Core Voltage | 1.5 V | — |
| Temperature na Operasyon | 0C to +85C (Commercial) | 0 C to +85 C (Commercial) |
| Packhaging | 780-ball FBGA (29 x 29 mm, 1 mm pitch) | FBGA-780 (29 x 29 mm, 1.0 mm pitch) |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Internal Operating Frequency (max) | 500 MHz | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| DSP Blocks | 12 (per family datasheet) | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| Configuration Modes | Passive Serial, Active Serial, JTAG | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, LVDS (per family datasheet) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant (N suffix) | Non-compliant (LEAD FR finish per AiPCBA datasheet) |
| Lead-Free | Yes | — |
| Speed Grade | C5 | — |
| Logic Elements (LEs) | — | 10,570 |
| Configurable Logic Blocks (CLBs) | — | 1,200 |
| Embedded Memory | — | 920 Kbit (TriMatrix) |
| Core Supply Voltage | — | 1.5 V |
| I/O Supply Voltage | — | Multi-voltage (3.3 V / 2.5 V / 1.8 V LVTTL/LVCMOS, LVDS) |
| Maximum Internal Clock Frequency | — | 450.05 MHz |
| Pin / Ball Count | — | 780 |
| Logic Family | — | CMOS |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous |
| Lead Finish | — | SnPb (LEAD FR / non-RoHS variant) |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |