EP1S10F780C7N vs EP1S10F780I6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F780C7N sa pamamagitan ng Intel at EP1S10F780I6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP1S10F780I6 - Stratix FPGA, 10570 Cells, 780-BGA | Altera/Intel
EP1S10F780I6 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1S10F780C7N | EP1S10F780I6 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | Stratix | Stratix |
| Logic Elements (LEs) | 10,570 | — |
| Embedded Memory | 920 Kbits (TriMatrix: MLAB, M512, M4K) | — |
| Embedded Multipliers | Yes (DSP blocks) | — |
| PLLs / DLLs | 6 PLL + DLL blocks | — |
| User I/O Count | Up to 426 | — |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Packhaging | FBGA-780 (29 × 29 mm, 1.0 mm pitch) | 780-ball FineLine BGA (FBGA-780), 29 x 29 mm, 1.0 mm pitch |
| Temperature na Operasyon | 0°C to 85°C (Commercial) | — |
| Speed Grade | C7 | 6 |
| Process Technology | 0.13 μm CMOS, 1.5 V core | CMOS |
| I/O Standards Supported | LVDS, LVPECL, SSTL, HSTL, LVCMOS, LVTTL | — |
| Configuration Modes | AS, PS, JTAG | Passive Serial (PS), Fast Passive Parallel (FPP), JTAG |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status not confirmed in verified data] | Compliant (lead-free FBGA package) |
| Logic Elements / Cells | — | 10,570 cells |
| Configurable Logic Blocks (CLBs) | — | 1,200 |
| Logic Array Blocks (LABs) | — | 1,057 |
| Embedded Memory (RAM bits) | — | 920,448 bits |
| Maximum User I/Os | — | 426 |
| Maximum Operating Frequency | — | 450 MHz |
| Operating Temperature (Industrial, I suffix) | — | -40C to +100C |
| PLLs | — | 8 |