EP1S20B672C6 vs EP1S20B672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20B672C6 sa pamamagitan ng Intel at EP1S20B672C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20B672C6 | EP1S20B672C7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix | Stratix (original) |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 18,460 | — |
| Embedded Memory Bits | 1,669,248 | 1,669,248 bits |
| User I/O Count | 426 | — |
| Packhaging | 672-ball FineLine BGA (672-BBGA) | — |
| Package Dimensions | 35 mm x 35 mm | — |
| Ball Pitch | 1.27 mm | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Speed Grade | C6 | -7 |
| Temperature na Operasyon | 0 C to 85 C (commercial) | 0 °C to 85 °C (Commercial Extended) |
| Maximum Internal Frequency | 450.05 MHz | — |
| Logic Family | CMOS | CMOS |
| Configuration Method | PS / PPS / PPA / JTAG | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Series | — | Stratix |
| Logic Elements (LEs) | — | 18,460 |
| LABs / CLBs | — | 1,846 |
| Maximum User I/O | — | 426 |
| Number of Pins / Balls | — | 672 |
| Package Type | — | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) |
| Supply Voltage (Core, VCCINT) | — | 1.5 V |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |