EP1S20B672C6 vs EP1S25B672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20B672C6 sa pamamagitan ng Intel at EP1S25B672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20B672C6 | EP1S25B672C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix | Stratix |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 18,460 | — |
| Embedded Memory Bits | 1,669,248 | — |
| User I/O Count | 426 | — |
| Packhaging | 672-ball FineLine BGA (672-BBGA) | 672-BGA, 35 x 35 mm, 1.27 mm pitch |
| Package Dimensions | 35 mm x 35 mm | — |
| Ball Pitch | 1.27 mm | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Speed Grade | C6 | C7 (commercial, slowest bin) |
| Temperature na Operasyon | 0 C to 85 C (commercial) | 0 C to 85 C |
| Maximum Internal Frequency | 450.05 MHz | 420.17 MHz |
| Logic Family | CMOS | CMOS |
| Configuration Method | PS / PPS / PPA / JTAG | SRAM-based (volatile, requires config device) |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Logic Cells | — | 25,660 |
| Logic Array Blocks (LABs) | — | 2,566 |
| Embedded Memory (bits) | — | 1,944,576 |
| Maximum User I/O | — | 473 |
| Core Voltage | — | 1.5 V |
| Number of PLLs | — | [DATA_NEEDED: PLL count] |
| Bilang ng Pin | — | 672 |
| Uri ng Pagpapasok | — | Surface Mount |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |