EP1S20F672C6 vs EP1S25F672C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672C6 sa pamamagitan ng Altera at EP1S25F672C6 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20F672C6 | EP1S25F672C6 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Manufacturer | Altera (now Intel) | — |
| Series | Stratix | — |
| Family | Stratix (first generation) | Stratix |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Logic Elements (LEs) | 18,460 | — |
| Logic Array Blocks (LABs) | 1,846 | — |
| Embedded Memory Bits | 1,669,248 | — |
| Maximum User I/Os | 426 | — |
| Packhaging | 672-ball FineLine BGA | 672-BBGA (FineLine BGA, 35 x 35 mm, 1.27 mm pitch) |
| Package Code | F672 | — |
| Speed Grade | C6 | 6 |
| Temperature na Operasyon | 0°C to +85°C (Commercial) | 0C to +85C (Commercial) |
| Volte ng Pagbibigay | Core 1.5 V, I/O programmable | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Logic Elements | — | 25,660 |
| Configurable Logic Blocks (CLBs) | — | 2,852 |
| Total RAM Bits | — | 1,944,576 |
| DSP Blocks | — | 14 |
| Maximum User I/O | — | 473 |
| Core Voltage | — | 1.5 V |
| Logic Family | — | CMOS |
| Configuration Method | — | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| PLL Count (Maximum) | — | 12 (including enhanced PLLs) |