EP1S20F672C6N vs EP1S20F672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672C6N sa pamamagitan ng Intel at EP1S20F672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20F672C6N | EP1S20F672C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Family | Stratix | Altera Stratix FPGA |
| Logic Elements | 18,460 | — |
| Total RAM Bits | 1,669,248 | — |
| User I/O Count | 426 | — |
| Packhaging | 672-BBGA (FineLine BGA) 35 x 35 mm | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) |
| Package Pitch | 1.27 mm | — |
| Core Voltage | 1.5 V | — |
| Logic Family | CMOS | CMOS, SRAM-based |
| Temperature na Operasyon | 0 C to 85 C (commercial) | 0C to 85C (commercial) |
| Speed Grade | -6 | C7 |
| Configuration Mode | PS, FPP, JTAG | — |
| Embedded DSP Blocks | Yes (36 x 36-bit multipliers) | — |
| TriMatrix Memory | M512, M4K, M-RAM blocks | — |
| PLLs | 12 (4 enhanced) | — |
| Global Clock Networks | 16 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead Free | Yes | — |
| Tindminan RoHS | Compliant | unknown |
| Series | — | Stratix |
| Logic Elements (LEs) | — | 18,460 |
| Embedded Memory Bits | — | 1,669,248 |
| User I/O Pins | — | 426 |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Core Supply Voltage | — | 1.5 V |
| Configuration Modes | — | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Clock PLLs | — | Up to 10 |