EP1S20F672C7 vs EP1S20F672I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672C7 sa pamamagitan ng Intel at EP1S20F672I7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera
EP1S20F672I7 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1S20F672C7 | EP1S20F672I7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Series | Stratix | — |
| Family | Altera Stratix FPGA | Stratix (first generation) |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Embedded Memory Bits | 1,669,248 | — |
| User I/O Pins | 426 | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: exact DSP block count] |
| Packhaging | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch |
| Logic Family | CMOS, SRAM-based | CMOS |
| Core Supply Voltage | 1.5 V | — |
| Temperature na Operasyon | 0C to 85C (commercial) | -40C to +85C (industrial grade, I7 suffix) |
| Speed Grade | C7 | — |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | Passive Serial, Passive Parallel, JTAG |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Level ng MSL | [DATA_NEEDED: MSL level] | unknown |
| Tindminan RoHS | unknown | unknown |
| Clock PLLs | Up to 10 | — |
| Maximum RAM Bits | — | 1,669,248 |
| Maximum User I/Os | — | 426 |
| Supply Voltage (VCCINT core) | — | 1.5 V |
| Number of Pins / Balls | — | 672 |
| Clock Management PLLs | — | [DATA_NEEDED: PLL count] |
| Lead-Free / Finish | — | SnPb (e0 per Partstack datasheet extract) |
| Status | — | Last Time Buy (per distributor notices) |