EP1S20F780C6N vs EP1S30F780C6GA Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F780C6N sa pamamagitan ng Intel at EP1S30F780C6GA sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20F780C6N | EP1S30F780C6GA |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix | Stratix FPGA |
| Manufacturer | Intel (formerly Altera) | — |
| Process Technology | 130 nm CMOS | 0.13 um |
| Logic Elements (LEs) | 18,460 | — |
| Configurable Logic Blocks (CLBs) | 2,132 | — |
| Embedded Memory Bits | 1,669,248 | — |
| Uri ng Memory | TriMatrix (M512 / M4K / M-RAM blocks) | — |
| DSP Blocks | Embedded 9x9 multiplier blocks | Integrated dedicated multipliers |
| Maximum User I/O Pins | 586 | — |
| Packhaging | 780-ball FC-FBGA (Fine-pitch BGA) | — |
| Package Dimensions | 29 x 29 mm, 1.0 mm pitch | — |
| Core Supply Voltage | 1.5 V | — |
| Temperature na Operasyon | 0 C to +85 C (commercial) | [DATA_NEEDED: industrial/commercial range] |
| Speed Grade | C6 (6 ns pin-to-pin delay class) | — |
| Maximum Internal Frequency | 450.05 MHz | — |
| Lead-Free / RoHS | Yes (lead-free) | — |
| Configuration Methods | PS, PPS, PPA, JTAG via EPC configuration device | — |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL, PCI, PCI-X | — |
| Series | — | Stratix |
| Logic Elements | — | 32,470 |
| Total RAM Bits | — | 3,317,184 |
| Number of I/O | — | 597 (maximum user I/O) |
| Core Voltage | — | 1.425 V to 1.575 V |
| Packhaging / Kaso | — | 780-BBGA, FCBGA |
| Supplier Device Package | — | 780-FBGA (29 x 29 mm) |
| Uri ng Pagpapasok | — | Surface Mount |
| PLL Count | — | Multiple (per Stratix family) |
| Configuration Memory | — | SRAM-based, volatile |
| Tindminan RoHS | — | [DATA_NEEDED] |
| Lead-Free Status | — | [DATA_NEEDED] |
| Level ng MSL | — | [DATA_NEEDED] |
| Architecture | — | Altera Stratix (programmable logic + TriMatrix memory + DSP blocks) |