EP1S25F672C5N vs EP1S25F672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S25F672C5N sa pamamagitan ng Intel at EP1S25F672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S25F672C5N | EP1S25F672C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | Stratix | — |
| Series | EP1S25 | Stratix |
| Logic Elements (Cells) | 25,660 | — |
| Number of CLBs | 2,566 | — |
| Number of Logic Cells / Gates | [DATA_NEEDED: total system gates] | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Maximum Internal Frequency | 500 MHz | — |
| Core Supply Voltage | 1.5 V (nominal) | — |
| Number of I/O Pins | 473 user I/O | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Package Type | FineLine BGA (FBGA) | — |
| Package Pin Count | 672 | — |
| Ball Pitch | 1.00 mm | — |
| Hanay ng Temperature na Operasyon | 0 °C to +85 °C (commercial) | — |
| Speed Grade | C5 | C7 (-7 commercial) |
| Lead-Free (Pb-Free) | Yes (suffix "N") | — |
| Configuration Method | SRAM-based, programmable via JTAG / Passive Serial / Fast Passive Parallel | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance] |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements (LEs) | — | 25,660 |
| Total RAM Bits | — | 1,944,576 |
| Configurable Logic Blocks (CLBs) | — | 2,852 |
| User I/O Count | — | 473 |
| Packhaging | — | 672-BBGA (FBGA), 35 x 35 mm, 1.27 mm pitch |
| Core Voltage | — | 1.5 V |
| Maximum Core Frequency | — | 420 MHz |
| Temperature na Operasyon | — | 0 °C to +85 °C (commercial) |
| Embedded Multipliers (18x18) | — | 224 |
| TriMatrix Memory Blocks | — | Yes (MRAM / M512 / M4K) |
| DLLs | — | 6 |
| PLLs | — | 2 |