EP1S25F672C6 vs EP1S20F672C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S25F672C6 sa pamamagitan ng Intel at EP1S20F672C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S25F672C6 | EP1S20F672C6 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix | Stratix (first generation) |
| Logic Elements | 25,660 | — |
| Configurable Logic Blocks (CLBs) | 2,852 | — |
| Total RAM Bits | 1,944,576 | — |
| DSP Blocks | 14 | — |
| Maximum User I/O | 473 | — |
| Packhaging | 672-BBGA (FineLine BGA, 35 x 35 mm, 1.27 mm pitch) | 672-ball FineLine BGA |
| Core Voltage | 1.5 V | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Temperature na Operasyon | 0C to +85C (Commercial) | 0°C to +85°C (Commercial) |
| Logic Family | CMOS | — |
| Speed Grade | 6 | C6 |
| Configuration Method | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| PLL Count (Maximum) | 12 (including enhanced PLLs) | — |
| Manufacturer | — | Altera (now Intel) |
| Series | — | Stratix |
| Logic Elements (LEs) | — | 18,460 |
| Logic Array Blocks (LABs) | — | 1,846 |
| Embedded Memory Bits | — | 1,669,248 |
| Maximum User I/Os | — | 426 |
| Package Code | — | F672 |
| Volte ng Pagbibigay | — | Core 1.5 V, I/O programmable |