EP1S25F672C8 vs EP1S25F672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S25F672C8 sa pamamagitan ng Intel at EP1S25F672C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S25F672C8 | EP1S25F672C7N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix | — |
| Logic Elements | 25,660 | — |
| Logic Array Blocks (LABs) | 2,566 | 2,566 |
| User I/Os | 473 | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Core Supply Voltage | 1.5 V | — |
| Maximum Operating Frequency | 357.14 MHz | — |
| Packhaging | 672-ball FineLine BGA (FBGA) | 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch |
| Package Dimensions | 35 x 35 mm, 1.27 mm pitch | — |
| Speed Grade | C8 (commercial, -8) | — |
| Temperature na Operasyon | 0 C to +85 C (commercial) | 0 °C to 85 °C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL Level] | [DATA_NEEDED: MSL rating] |
| Tindminan RoHS | [DATA_NEEDED: RoHS Status] | [DATA_NEEDED: confirm from product page] |
| Logic Family | CMOS | — |
| Configuration Method | JTAG / Altera configuration device | JTAG / Passive Serial / Active Serial |
| Device Family | — | Stratix |
| Logic Elements (LEs) | — | 25,660 |
| Embedded Memory Bits | — | 1,944,576 |
| Maximum User I/O | — | 473 |
| Number of I/O Pins | — | 672 (BGA balls) |
| Core Supply Voltage (VCCINT) | — | 1.5 V |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] |