EP1S25F672I7N vs EP1S25F672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S25F672I7N sa pamamagitan ng Intel at EP1S25F672C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S25F672I7N | EP1S25F672C7N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Stratix | — |
| Logic Elements | 25,660 | — |
| Embedded Memory | 1.9 Mbit TriMatrix | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Core Supply Voltage | 1.5 V | — |
| Packhaging | 672-ball FineLine BGA, 35 x 35 mm, 1.27 mm pitch | 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch |
| User I/O Pins | 473 | — |
| Maximum Operating Frequency | 420 MHz (internal) | — |
| Temperature na Operasyon | 0 °C to 85 °C (Industrial) | 0 °C to 85 °C (commercial) |
| Speed Grade | -7 | — |
| Uri ng Pagpapasok | Surface Mount (SMT) | Surface Mount |
| Configuration Mode | Passive Serial / Fast Passive Parallel / JTAG | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: confirm from product page] |
| DSP Blocks | Dedicated 18 x 18 multipliers | — |
| Device Family | — | Stratix |
| Logic Elements (LEs) | — | 25,660 |
| Logic Array Blocks (LABs) | — | 2,566 |
| Embedded Memory Bits | — | 1,944,576 |
| Maximum User I/O | — | 473 |
| Number of I/O Pins | — | 672 (BGA balls) |
| Core Supply Voltage (VCCINT) | — | 1.5 V |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] |
| Configuration Method | — | JTAG / Passive Serial / Active Serial |