EP1S25F780I6N vs EP1S25F780C5N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1S25F780I6N sa pamamagitan ng Intel at EP1S25F780C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1S25F780I6N EP1S25F780C5N
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Stratix Stratix
Logic Elements 25,660 25,660
Logic Array Blocks (LABs) 2,566 2,566
Total RAM Bits 1,944,576 —
User I/O Pins 597 —
Packhaging 780-BBGA (FineLine BGA, 29 x 29 mm, 1.0 mm pitch) 780-ball FBGA, 29 x 29 mm, 1.0 mm pitch
Process Technology 130 nm CMOS 130 nm CMOS
Core Voltage 1.5 V —
Speed Grade 6 (I6 - industrial) —
Temperature na Operasyon 0C to 85C (industrial) 0 C to 85 C (Commercial Extended)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount (BGA)
Level ng MSL 3 (per Partstack listing) [DATA_NEEDED: MSL rating per JEDEC J-STD-020]
Lead Free Yes (per Ampheo listing) —
Tindminan RoHS [DATA_NEEDED: rohs status] [DATA_NEEDED: confirm per specific reel lot]
DSP Blocks Yes (dedicated 9/18/36-bit multipliers) Dedicated multiplier/accumulator blocks
Embedded PLL Yes —
LVDS Support Yes (up to 840 Mbps per Altera datasheet family) —
Configuration Mode JTAG / Passive Serial / Fast Passive Parallel (per Stratix family) —
Maximum User I/O — 597
Core Supply Voltage — 1.5 V
Embedded Memory — TriMatrix memory blocks, up to ~1.92 Mbits total
PLLs — 4
I/O Banks — 12
Maximum Frequency (internal) — up to 500 MHz logic, 420 MHz DSP
Supported I/O Standards — LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, PCI, PCI-X
Configuration Modes — Passive Serial, Passive Parallel Sync/Async, JTAG

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita