EP1S40F1020C5 vs EP1S40F1020C5DM Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S40F1020C5 sa pamamagitan ng Intel at EP1S40F1020C5DM sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S40F1020C5 | EP1S40F1020C5DM |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix | — |
| Series | Stratix I | Stratix |
| Logic Elements | 41,250 | 41,250 |
| Logic Array Blocks (LABs) | 4,125 | — |
| Maximum User I/Os | 773 | — |
| Embedded Memory | 3.4 Mbits (TriMatrix) | 3,423 Kbits TriMatrix |
| DSP Blocks | Yes (dedicated hardware multipliers) | 12 (up to 28.8 GMACS at 200 MHz) |
| Process Technology | 130 nm | 0.13 µm CMOS |
| Core Voltage | 1.425 V to 1.575 V | — |
| Speed Grade | C5 | — |
| Packhaging | 1020-ball FC-FBGA (33 mm x 33 mm) | 1020-ball FineLine BGA (33 mm x 33 mm, 1.0 mm pitch) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Temperature na Operasyon | 0C to +85C (Commercial) | 0C to +85C (commercial) |
| Maximum Internal Clock | up to 500 MHz | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL, HSTL, LVDS, PCI | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Product Type | — | FPGA - Field Programmable Gate Array |
| User I/O Count | — | 773 |
| Number of LABs/CLBs | — | 4125 |
| Number of PLLs | — | 6 (8 outputs each) |
| Number of Clock Networks | — | 16 |
| Core Voltage VCCINT | — | 1.5 V |
| I/O Voltage VCCIO | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Configuration Modes | — | PS, PPS, PPA, JTAG |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |