EP1S40F1020C5GA vs EP1S40B956C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S40F1020C5GA sa pamamagitan ng Intel at EP1S40B956C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S40F1020C5GA | EP1S40B956C6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | Stratix | Stratix |
| Logic Elements (LE) | 41,250 | — |
| Total RAM Bits | 3,423,744 | — |
| User I/O Count | 773 | — |
| Packhaging | 1020-BBGA (FineLine BGA) | 956-ball FineLine BGA (FCBGA) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (Commercial) | 0 °C to +85 °C (Commercial) |
| Speed Grade | C5 | C6 (commercial, mid-speed) |
| Process Node | 0.13 µm CMOS with 9-layer metal | — |
| Supply Voltage (Core) | [DATA_NEEDED: VCCINT value] | — |
| I/O Bank Count | [DATA_NEEDED: bank count] | — |
| DSP Blocks | Embedded multiplier blocks (count per Stratix datasheet family) | — |
| PLL Count | Up to 12 enhanced PLLs (per Stratix family) | — |
| High-Speed Transceivers | Up to 12 channels (per Stratix family, variant dependent) | — |
| Configuration Method | JTAG, Passive Serial, Altera EPC device | — |
| Tindminan RoHS | Unknown - non-GA suffix commercial part | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes (per Altera/Intel policy at release) | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Family | — | Altera Stratix (1st generation) |
| Process Technology | — | 0.13 µm CMOS |
| Logic Elements (LEs) | — | 41,250 |
| Logic Array Blocks (LABs) | — | 4,125 |
| Embedded Memory | — | 3,423,744 bits (~3.4 Mbit) |
| Maximum User I/O | — | 683 |
| Volte ng Pagbibigay | — | 1.425 V to 1.575 V (1.5 V nominal) |
| Package Dimensions | — | 40 mm x 40 mm |
| Ball Pitch | — | 1.27 mm |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Active Serial |