EP1S40F780C8N vs EP1S40F780C5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S40F780C8N sa pamamagitan ng Intel at EP1S40F780C5 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S40F780C8N | EP1S40F780C5 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Stratix | Stratix |
| Series | EP1S | Stratix (EP1S40) |
| Logic Elements | 41,250 | — |
| Embedded Memory | 3,423,744 bits | — |
| Embedded Multipliers | 615 (18-bit x 18-bit) | — |
| Packhaging | 780-ball FCBGA (FineLine BGA), 29 mm x 29 mm, 1 mm pitch | 780-ball FBGA (FBGA-780), 29 x 29 mm, 1.0 mm pitch |
| Logic Family | CMOS | — |
| Supply Voltage (Core) | 1.5 V | — |
| Speed Grade | C8 (commercial) | — |
| Temperature na Operasyon | 0 °C to +85 °C | — |
| I/O Standard Support | LVDS, LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X | — |
| Maximum LVDS Data Rate | 840 Mbps | — |
| PLL Blocks | Up to 12 | — |
| Uri ng Memory | TriMatrix (MRAM, M512, M4K blocks) | — |
| External Memory Interface | DDR, DDR-II, QDR, SDRAM | — |
| Configuration Method | Passive serial, Fast passive parallel, JTAG | — |
| Design Software | Quartus II | — |
| Tindminan RoHS | Compliant | Non-compliant per ICComponents listing |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Logic Elements (LE) | — | 41,250 |
| Adaptive Logic Modules (ALM) | — | [DATA_NEEDED: ALM count - Stratix I uses LE, not ALM] |
| Configurable Logic Blocks (CLBs) | — | 4,697 |
| Embedded RAM Bits | — | 3,423,744 bits (3.4 Mbit) |
| Embedded Multiplier / DSP Blocks | — | 12 DSP blocks |
| Maximum User I/O | — | 615 |
| Process Technology | — | 130 nm CMOS |
| Temperature Grade | — | Commercial Extended |
| Configuration Mode | — | Active Serial (AS), Passive Serial (PS), JTAG |
| Supply Voltage - Core | — | 1.5 V (typical) |
| I/O Bank Voltage | — | [DATA_NEEDED: supported VCCIO levels] |