EP1S60F1020 vs EP1S60F1020C6NAA Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S60F1020 sa pamamagitan ng Altera at EP1S60F1020C6NAA sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S60F1020 | EP1S60F1020C6NAA |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | Stratix | EP1S60 |
| Family | Altera Stratix (EP1S) | Stratix |
| Process Technology | 0.13 um CMOS | — |
| Logic Elements (LEs) | 57,120 | — |
| Logic Array Blocks (LABs) | 5,712 | — |
| Total RAM Bits | 5,215,104 | 5,215,104 |
| Embedded Multipliers (DSP Blocks) | [DATA_NEEDED: DSP block count] | — |
| User I/Os | 773 | — |
| PLLs | [DATA_NEEDED: PLL count, nominally 12 for Stratix EP1S60] | — |
| Packhaging | 1020-BGA (FineLine FBGA) | 1020-BBGA (FineLine BGA), 33x33 mm, 1.0 mm pitch |
| Core Voltage | 1.5 V | — |
| Operating Temperature (base part) | Commercial (0C to +85C) | — |
| Speed Grade (base part) | [DATA_NEEDED: trailing suffix needed for explicit grade] | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | [DATA_NEEDED: verify per part suffix] | — |
| I/O Standard Support | LVDS, LVPECL, SSTL, HSTL, PCI/PCI-X | — |
| Configuration Memory | SRAM-based, requires external configuration device | — |
| Logic Elements | — | 57,120 |
| Embedded Multipliers | — | 192 (18x18) |
| Maximum User I/O Pins | — | 773 |
| Number of LABs/CLBs | — | 4,510 |
| Number of Logic Cells | — | 57,120 |
| Temperature na Operasyon | — | 0C to +85C (commercial) |
| Process Node | — | 0.13 µm CMOS |
| Voltage - Core | — | 1.5 V |
| Voltage - I/O | — | 1.5V / 1.8V / 2.5V / 3.3V (MultiVolt) |
| Speed Grade | — | C6 |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Configuration Scheme | — | Passive Serial / Fast Passive Parallel / JTAG |
| Number of PLLs | — | 12 |
| Global Clocks | — | 40 |