EP1S80B956C6 vs EP1S80B956C6AB Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S80B956C6 sa pamamagitan ng Altera at EP1S80B956C6AB sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S80B956C6 | EP1S80B956C6AB |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix | Stratix |
| Logic Elements (LE) | 79,040 | — |
| Logic Array Blocks (LAB) | 7,904 | — |
| Total Memory Bits | 7,427,520 (TriMatrix: M512 + M4K + M-RAM) | — |
| Embedded Memory | 6.336 Mbit | — |
| DSP Blocks | 22 | Embedded DSP blocks (per Stratix family) |
| Maximum User I/O | 683 | — |
| Supply Voltage - Core | 1.425 V to 1.575 V | — |
| Process Technology | 130 nm CMOS | 130 nm |
| Packhaging | 956-BBGA, FCBGA, 40x40 mm | 956-ball FCBGA |
| Temperature na Operasyon | 0C to 85C (TJ, commercial) | [DATA_NEEDED: operating temperature range] |
| Speed Grade | -6 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Maximum Transceiver Rate | [DATA_NEEDED: high-speed transceiver data rate, GHz] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Logic Elements (LEs) | — | 79,040 |
| Logic Cells | — | 79,040 |
| Core Voltage | — | 1.5 V |
| Maximum Operating Frequency | — | 450.05 MHz |
| User I/O Pins | — | 683 |
| Memory Blocks | — | TriMatrix embedded RAM |
| PLLs | — | Multiple PLLs for clock management |
| Configuration Method | — | SRAM-based, configured via JTAG or passive/active serial |
| Manufacturer | — | Intel (formerly Altera) |