EP1S80F1020C6N vs EP1S60F1020C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S80F1020C6N sa pamamagitan ng Intel at EP1S60F1020C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S80F1020C6N - Stratix 79,040 Logic Elements FPGA | Intel (Altera) | 1020-BGA
EP1S80F1020C6N NrndPagsanggunian na paghahambing
| Parametro | EP1S80F1020C6N | EP1S60F1020C6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Stratix | Stratix |
| Logic Cells / Logic Elements | 79,040 | — |
| Equivalent Gate Count | 7,427,520 | — |
| Number of LABs/CLBs | 7904 | — |
| Number of User I/Os | 773 | — |
| Packhaging | 1020-ball FBGA (FC-FBGA), 33 x 33 mm, 1 mm pitch | — |
| Process Technology | 130 nm CMOS | — |
| Core Supply Voltage | 1.5 V | — |
| Temperature na Operasyon | 0C to 85C (Commercial) | 0°C to +85°C (Commercial) |
| Speed Grade | C6 | C6 (mid-tier) |
| Uri ng Pagpapasok | Surface Mount (SMT) | Surface Mount (BGA) |
| Operating Frequency (typ.) | 450 MHz (Stratix family max) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (per 'N' suffix) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | [DATA_NEEDED: MSL level] | — |
| Configuration Memory Interface | Serial (EPCS) or parallel - per Stratix family | — |
| Family | — | Stratix (EP1S) |
| Logic Elements (LEs) | — | 57,120 |
| Logic Cells | — | 6,570 blocks (per chipdig datasheet summary) |
| Embedded RAM (Total Bits) | — | 5,215,104 bits |
| Embedded Multipliers | — | 773 (18x18) |
| Maximum User I/O Pins | — | Per datasheet, package-dependent (F1020 variant) |
| Package Type | — | 1020-ball FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch |
| Logic Family / Process | — | CMOS, 0.13 µm |
| Volte ng Pagbibigay | — | Per datasheet (Stratix Device Handbook Vol. 1) |
| Lead-Free / Pb-Free | — | Yes (suffix 'N') |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Configuration | — | JTAG / Passive Serial / Fast Passive Parallel via MSEL pins |
| PLL Count | — | 12 (per Stratix family datasheet) |
| Memory Block Types | — | TriMatrix (M512, M4K, M-RAM) |