EP1SGX40DF1020I7 vs EP1SGX40DF1020I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1SGX40DF1020I7 sa pamamagitan ng Altera at EP1SGX40DF1020I7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP1SGX40DF1020I7 - 41,250 LEs Stratix GX FPGA, 1.5V FC-FBGA-1020 | Altera
EP1SGX40DF1020I7 ObsoletePagsanggunian na paghahambing
| Parametro | EP1SGX40DF1020I7 | EP1SGX40DF1020I7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 41,250 | — |
| Configurable Logic Blocks (CLBs) | 4,125 | 4,125 |
| Process Technology | 130 nm CMOS | 130 nm |
| Nominal Core Supply Voltage | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | 1.425 V to 1.575 V |
| Packhaging | 1020-ball FC-FBGA | — |
| Terminal Form | Ball | Ball |
| Package Shape | Square | Square |
| Grading of Temperature | Military (I7 grade) | — |
| Technology | CMOS | — |
| Temperature na Operasyon | -40 °C to +100 °C (I7 grade per family datasheet) | 0 C to 85 C (commercial) |
| Combinatorial CLB Delay | 9.48 ns (per family datasheet) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Device Model | — | EP1SGX40 |
| Logic Cells | — | 41,250 |
| Logic Family | — | CMOS |
| Nominal Supply Voltage | — | 1.5 V |
| Package Type | — | FC-FBGA, 33 x 33 mm, 1 mm pitch |
| Number of Pins / Balls | — | 1020 |
| Package Code | — | BGA |
| Maksimum na Taktiko ng Oras | — | 4385.97 MHz |
| Combinatorial Delay | — | [DATA_NEEDED: tPD] |
| Configuration Modes | — | JTAG, Passive Serial, Fast Passive Parallel |