EP20K1000CF33I8N vs EP20K100FC324-1V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K1000CF33I8N sa pamamagitan ng Altera at EP20K100FC324-1V sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K1000CF33I8N | EP20K100FC324-1V |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Logic Elements | 38,400 cells | — |
| System Gates | 1,000,000 (approx.) | — |
| Maximum Internal Clock Frequency | 301.21 MHz | — |
| Propagation Delay | 1.79 ns | — |
| Number of Logic Elements / Cells | 38,400 | 4160 |
| Process Technology | 0.15 µm CMOS | — |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Number of I/O Pins | 700 user I/O | — |
| Bilang ng Pins | 1020 | — |
| Package Type | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) | — |
| Temperature na Operasyon | -40 °C to +85 °C (industrial) | 0C to +85C (commercial) |
| Embedded Memory | Dual-port RAM via ESB blocks | — |
| PLL Count | 4 | — |
| Configuration Interface | IEEE 1149.1 JTAG, EPC serial/parallel | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Speed Grade | I8 | -1V (commercial) |
| Series | — | APEX-20K® |
| Total RAM Bits | — | 53248 |
| Number of Gates (typical) | — | 100000 |
| Number of I/O | — | 252 |
| Number of LABs/CLBs | — | [DATA_NEEDED: number of Logic Array Blocks] |
| Number of EABs | — | [DATA_NEEDED: number of Embedded Array Blocks] |
| Supply Voltage - Core (VCCINT) | — | 2.375 V to 2.625 V |
| Supply Voltage - I/O (VCCIO) | — | 3.0 V / 3.3 V / 5.0 V tolerant (per I/O standard) |
| Packhaging / Kaso | — | 324-FBGA (FineLine BGA, 19x19 mm) |
| Supplier Device Package | — | 324-FBGA |
| Number of PLLs | — | 4 |
| I/O Standards Supported | — | LVCMOS, LVTTL, PCI, SSTL, GTL+, HSTL |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| Programming Interface | — | JTAG (IEEE 1149.1) / in-system |