EP20K1000CF672C7 vs EP20K1000CF672C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K1000CF672C7 sa pamamagitan ng Intel at EP20K1000CF672C8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K1000CF672C7 | EP20K1000CF672C8 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Device Type | FPGA (Field Programmable Gate Array) | Field Programmable Gate Array (FPGA) |
| System Gates | 1,000,000 (typical) | 1,000,000 |
| Logic Elements / Cells | 38400 | 38,400 |
| Maximum Internal Frequency | 375.94 MHz | — |
| Propagation Delay | 1.6 ns (typical) | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.15 um all-layer copper CMOS |
| Core Supply Voltage | 1.8 V | — |
| User I/O Count | 488 (some sources list 508) | — |
| Packhaging | 672-ball FC-FBGA (45 × 45 mm, 1.27 mm pitch) | 672-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | 0 °C to +85 °C (commercial, C suffix) | 0C to 85C (commercial) |
| Speed Grade | C7 (fastest) | — |
| Embedded Memory (EAB) | Embedded array blocks (RAM/CAM/ROM) | — |
| PLL Count | 4 | — |
| Configuration Interface | Passive Serial, JTAG (IEEE 1149.1), Fast Passive Parallel | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - part predates common RoHS reporting] | unknown (legacy part, verify on lot) |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | APEX 20KC |
| Embedded RAM | — | 327,680 bits |
| User I/Os | — | 488 (datasheet), 508 (per some distributor listings) |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Number of Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| Number of PLLs | — | 4 |
| Maximum User I/O Pins | — | 488 |
| Core Voltage (VCCINT) | — | 1.8 V (typical) |
| I/O Voltage (VCCIO) | — | Multi-voltage (LVTTL/LVCMOS/LVDS/SSTL/GTL+ compatible) |
| Propagation Delay (typical) | — | 1.6 ns |
| Configuration Mode | — | FPP / Passive Serial / JTAG |