EP20K1000CF672I8 vs EP20K1000CF672C8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K1000CF672I8 sa pamamagitan ng Intel at EP20K1000CF672C8N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K1000CF672I8 | EP20K1000CF672C8N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Manufacturer | Intel (formerly Altera) | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper |
| System Gates | 1,000,000 | — |
| Logic Elements / Cells | 38,400 | 38,400 |
| Packhaging | 672-pin FC-FBGA (FineLine BGA) | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA), 45 x 45 mm, 1.27 mm pitch |
| Ball Pitch | 1.00 mm | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | — |
| User I/O Count | 508 | — |
| Dedicated Inputs | 4 | — |
| Internal Frequency (max) | 301.21 MHz | — |
| Pin-to-Pin Logic Delay | 8 ns | — |
| Temperature na Operasyon | -40 °C to +85 °C (industrial, I suffix) | 0°C to 85°C (Commercial) |
| Uri ng Memory | SRAM-based (volatile) | — |
| Embedded Memory | Embedded Array Blocks (EABs) for dual-port RAM / FIFO | — |
| PLL Count | 4 | — |
| I/O Standards | LVTTL, LVCMOS, PCI, SSTL, HSTL | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Device Family | — | APEX 20KC |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Equivalent Gate Count | — | 1,000,000 gates |
| Embedded Memory (bits) | — | 327,680 |
| Number of I/Os | — | 488 to 508 |
| Number of Pins / Balls | — | 672 |
| Supply Voltage (Vccint) | — | 1.8 V |
| Internal Operating Frequency (max) | — | 301.21 MHz |
| Propagation Delay (typ.) | — | 1.6 ns to 1.79 ns |
| Architecture | — | MultiCore (LUT + embedded memory + product-term) |
| Lead-Free | — | [DATA_NEEDED: lead-free finish status] |
| Pin-to-Pin Compatibility | — | APEX 20KE family (same 672-ball BGA) |