EP20K100CF144C9 vs EP20K100FC144-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100CF144C9 sa pamamagitan ng Intel at EP20K100FC144-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K100CF144C9 EP20K100FC144-1
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family APEX-20K APEX-20K
Device Logic Elements 4,160 —
Typical Gates 100,000 100,000
Embedded System Blocks (ESBs) 4 —
Maximum User I/O Pins 93 —
Embedded RAM Bits 53,248 53,248
Packhaging 144-LQFP 144-LQFP
Pin Pitch 0.5 mm [DATA_NEEDED: confirm pitch, datasheet quotes 0.5 mm for LQFP-144] —
Configuration Method SRAM / JTAG (IEEE 1149.1) —
Core Voltage 2.5 V 2.5 V
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+ [DATA_NEEDED: full list per datasheet I/O chapter] —
Speed Grade C9 (commercial) -1 (slowest)
Operating Temperature (Commercial) 0C to +85C —
Uri ng Pagpapasok Surface Mount Surface Mount
Lead-Free / RoHS [DATA_NEEDED: not stated in distributor snippets] —
Series — APEX-20K
Logic Elements — 4,160
User I/O Pins — 93
Number of Logic Array Blocks (LABs) — [DATA_NEEDED: LAB count]
Number of Embedded System Blocks (ESBs) — [DATA_NEEDED: ESB count]
Number of Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count]
I/O Voltage — 3.3 V (PCI-compatible)
Temperature na Operasyon — [DATA_NEEDED: temperature grade]
Programmable Interface — JTAG / IEEE 1532 (ISP)
PCI Compliance — 3.3V PCI compliant
Tindminan RoHS — [DATA_NEEDED: RoHS compliance]

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