EP20K100CQ240C9 vs EP20K100CQ240C7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100CQ240C9 sa pamamagitan ng Intel at EP20K100CQ240C7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K100CQ240C9 EP20K100CQ240C7
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Series APEX 20K —
Family APEX 20K (SRAM-based FPGA) APEX-20K
Typical Gates 100,000 —
Logic Elements 4,160 53,248
Embedded Memory (RAM bits) 53,248 —
User I/O Pins 189 —
Number of PLLs 4 4 (per APEX-20K family datasheet)
Package Type 240-BQFP (QFP-240) 240-BFQFP
Temperature na Operasyon 0°C to +85°C (commercial) 0C to +85C (commercial)
Speed Grade C9 (-9 commercial) C7
Process Technology 0.22 µm CMOS SRAM —
Programming Method In-system SRAM (volatile) —
Configuration Method Serial/Passive Parallel/Byte-wide JTAG —
Supply Voltage (VCCINT) [DATA_NEEDED: VCCINT core voltage] —
Supply Voltage (VCCIO) [DATA_NEEDED: VCCIO I/O voltage] —
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL LVTTL, LVCMOS, PCI, GTL (per family datasheet)
JTAG (IEEE 1149.1) Support Yes —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] unknown
Device Type — FPGA (Field Programmable Gate Array)
System Gates — 100,000
Embedded Memory Bits — 4,160
Maximum User I/O Pins — 189
Supply Voltage - Core — [DATA_NEEDED: core voltage]
Embedded System Blocks (ESBs) — Yes (per APEX-20K family)
Lead-Free — unknown
Level ng MSL — [DATA_NEEDED: MSL rating]
Programming Tool — Altera Quartus / MAX+PLUS II (per family)

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