EP20K100CQ240C9 vs EP20K100QC240-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100CQ240C9 sa pamamagitan ng Intel at EP20K100QC240-1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K100CQ240C9 - APEX 20K FPGA 100K Gates 189 I/O QFP240 | Intel
EP20K100CQ240C9 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP20K100CQ240C9 | EP20K100QC240-1 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | APEX 20K | — |
| Family | APEX 20K (SRAM-based FPGA) | APEX 20K |
| Typical Gates | 100,000 | 100,000 |
| Logic Elements | 4,160 | — |
| Embedded Memory (RAM bits) | 53,248 | — |
| User I/O Pins | 189 | — |
| Number of PLLs | 4 | — |
| Package Type | 240-BQFP (QFP-240) | — |
| Temperature na Operasyon | 0°C to +85°C (commercial) | 0 °C to +85 °C (Commercial) |
| Speed Grade | C9 (-9 commercial) | -1 |
| Process Technology | 0.22 µm CMOS SRAM | 0.22 µm CMOS |
| Programming Method | In-system SRAM (volatile) | — |
| Configuration Method | Serial/Passive Parallel/Byte-wide JTAG | — |
| Supply Voltage (VCCINT) | [DATA_NEEDED: VCCINT core voltage] | — |
| Supply Voltage (VCCIO) | [DATA_NEEDED: VCCIO I/O voltage] | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL | — |
| JTAG (IEEE 1149.1) Support | Yes | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Logic Elements (LEs) | — | 4,160 |
| Maximum User I/O | — | 189 |
| Embedded RAM Bits | — | 53,248 |
| Core Supply Voltage | — | 2.5 V |
| Maximum Internal Frequency | — | 250 MHz |
| Packhaging | — | 240-pin PQFP (QFP-240) |
| Package Code | — | S-PQFP-G240 |
| Terminal Form | — | Gull Wing |
| Propagation Delay | — | 1.6 ns (per datasheet, typical) |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| Programming | — | In-system (SRAM-based) via Quartus / MAX+PLUS II |