EP20K100FC144-1 vs EP20K100FC144-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100FC144-1 sa pamamagitan ng Altera at EP20K100FC144-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K100FC144-1 | EP20K100FC144-2 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | APEX-20K | — |
| Family | APEX-20K | APEX-20K |
| Typical Gates | 100,000 | — |
| Logic Elements | 4,160 | 4,160 |
| Embedded RAM Bits | 53,248 | — |
| User I/O Pins | 93 | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Number of Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Number of Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | — |
| Core Voltage | 2.5 V | — |
| I/O Voltage | 3.3 V (PCI-compatible) | — |
| Speed Grade | -1 (slowest) | -2 |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | 0 C to 85 C (Commercial) |
| Packhaging | 144-LQFP | 144-TQFP (20x20 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmable Interface | JTAG / IEEE 1532 (ISP) | — |
| PCI Compliance | 3.3V PCI compliant | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs status] |
| Logic Array Blocks (LABs) | — | 416 |
| Embedded System Block (ESB) RAM | — | 53,248 bits |
| Maximum User I/O Pins | — | 93 |
| Core Supply Voltage (VCCINT) | — | 2.375 V to 2.625 V |
| Process Technology | — | 0.18 um CMOS |
| PLLs | — | 4 |
| JTAG (IEEE 1149.1) | — | Yes |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |