EP20K100FC324-2X vs EP20K100FC324-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100FC324-2X sa pamamagitan ng Altera at EP20K100FC324-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K100FC324-2X - APEX 20K FPGA 100K Gates 324-BGA | Intel / Altera
EP20K100FC324-2X Obsolete
Pagsanggunian na paghahambing
| Parametro | EP20K100FC324-2X | EP20K100FC324-2 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | APEX-20K | — |
| Logic Elements | 4,160 | — |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Maximum User I/O | 252 | — |
| Embedded RAM Bits | 53,248 | — |
| Operating Frequency (max) | 200 MHz | — |
| Propagation Delay | 1.6 ns | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 3.3 V (5 V tolerant I/O) | — |
| Packhaging | 324-ball FineLine BGA (FBGA) | 324-ball FBGA |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | 0 °C to +85 °C (Commercial) | 0°C to 85°C |
| Configuration Interface | JTAG (IEEE 1149.1) / Serial / Parallel | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | APEX 20K |
| Equivalent Gates | — | 100,000 |
| Logic Cells | — | 4,160 |
| Maximum User I/Os | — | 252 |
| Bilang ng Pin | — | 324 |
| Technology Node | — | 0.22 µm CMOS |
| Propagation Delay (tPD) | — | 1.6 ns |
| Internal Performance | — | 200 MHz |
| Configuration Method | — | JTAG / serial configuration PROM |
| Embedded Memory | — | Dual-port RAM blocks (ESB) |
| Programming Toolchain | — | Altera Quartus / MAX+PLUS II |