EP20K100QC240-1 vs EP20K100QC240-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K100QC240-1 sa pamamagitan ng Intel at EP20K100QC240-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K100QC240-1 | EP20K100QC240-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX 20K | — |
| Device Type | FPGA (Field-Programmable Gate Array) | Field Programmable Gate Array (FPGA) |
| Logic Elements (LEs) | 4,160 | — |
| Typical Gates | 100,000 | — |
| Maximum User I/O | 189 | — |
| Embedded RAM Bits | 53,248 | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | — |
| Maximum Internal Frequency | 250 MHz | 200 MHz |
| Speed Grade | -1 | -2 |
| Packhaging | 240-pin PQFP (QFP-240) | — |
| Package Code | S-PQFP-G240 | — |
| Terminal Form | Gull Wing | — |
| Propagation Delay | 1.6 ns (per datasheet, typical) | 3 ns |
| Temperature na Operasyon | 0 °C to +85 °C (Commercial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Programming | In-system (SRAM-based) via Quartus / MAX+PLUS II | — |
| Series | — | APEX-20K |
| Number of Logic Elements/Cells | — | 4160 |
| Number of LABs/CLBs | — | 416 |
| Number of User I/Os | — | 189 |
| Total RAM Bits | — | 53248 |
| Typical Gate Count | — | 100000 |
| Maximum System Gates | — | 263000 |
| Supply Voltage na Operasyon | — | 2.375 V to 2.625 V (2.5 V nominal) |
| Hanay ng Temperature na Operasyon | — | 0°C to 85°C (TJ) |
| Packhaging / Kaso | — | 240-BFQFP (PQFP-240) |
| Number of Pins / Terminals | — | 240 |
| Terminal Pitch | — | 0.5 mm |
| Technology / Process | — | CMOS, 0.22 µm |
| Tindminan RoHS | — | Unknown |