EP20K200BC356-2 vs EP20K100EBC356-3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200BC356-2 sa pamamagitan ng Intel at EP20K100EBC356-3N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K200BC356-2 | EP20K100EBC356-3N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20K | APEX-20KE |
| Device Family | APEX-20K (MultiCore PLD) | — |
| Logic Elements | 8,320 | — |
| Typical Gate Count | 200,000 gates | — |
| Embedded Memory | 106,496 bits | — |
| User I/Os | 277 | — |
| Logic Family | CMOS | — |
| Process Technology | 0.22 µm | 0.22 µm CMOS |
| Propagation Delay | 2.5 ns | 1.6 ns (speed grade -3N) |
| Core Supply Voltage | 2.5 V | 1.8 V |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0 °C to +85 °C |
| Packhaging | 356-LBGA (35 mm × 35 mm) | 356-LBGA (Ball Grid Array) |
| Speed Grade | -2 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Maximum Frequency | 200 MHz | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs_status] |
| Family | — | APEX 20K |
| Logic Elements / Cells | — | 4160 |
| System Gates | — | 100,000 |
| Embedded Memory (bits) | — | 53,248 |
| Embedded System Blocks (ESBs) | — | 26 |
| Maximum User I/Os | — | 246 |
| Bilang ng Pins | — | 356 |
| Package Dimensions | — | 45 x 45 mm |
| Ball Pitch | — | 1.27 mm |
| Maximum Internal Frequency | — | 250 MHz |
| Programmable Interface | — | JTAG (IEEE 1149.1) |
| I/O Standards Supported | — | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ |