EP20K200CF484C8ES vs EP20K200CF484C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200CF484C8ES sa pamamagitan ng Altera at EP20K200CF484C7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K200CF484C8ES | EP20K200CF484C7 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | APEX-20KC | APEX 20KC |
| Family | APEX 20K | APEX 20KC |
| Logic Elements | 8,320 | — |
| System Gates | 200,000 | — |
| Embedded Memory (RAM bits) | 106,496 | — |
| Number of Logic Array Blocks (LABs) | 104 | — |
| Number of Embedded System Blocks (ESBs) | 13 | — |
| User I/O Pins (max) | 376 | — |
| PLLs | 4 | — |
| Core Voltage | 1.8 V | — |
| Speed Grade | C8 (-8 commercial) | C7 (commercial, mid-performance) |
| Packhaging | 484-pin FBGA (FineLine BGA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (commercial) | 0°C to +85°C |
| Process Node | 0.18 micron CMOS | — |
| Configuration Interface | JTAG (IEEE 1149.1) / Altera serial | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL, SSTL, HSTL, AGP | — |
| Lead Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Number of Logic Elements (LEs) | — | 8,320 |
| Number of Gates | — | 200,000 |
| Total RAM Bits | — | 106,496 |
| Number of I/O | — | 376 |
| Supply Voltage - Core | — | 1.71 V to 1.89 V |
| Process Technology | — | 0.15 µm CMOS, Copper interconnect |
| Maximum Internal Frequency | — | 375.94 MHz |
| LVDS Support | — | Yes |
| Packhaging / Kaso | — | 484-BBGA (FineLine BGA, 23×23 mm) |
| Supplier Device Package | — | 484-FBGA |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Configuration Memory | — | SRAM-based (volatile, requires configuration device) |