EP20K200EBC652-1X vs EP20K1000EBC652-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200EBC652-1X sa pamamagitan ng Altera at EP20K1000EBC652-2X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K200EBC652-1X - APEX 20KE FPGA 200K 832 Macro Cells 652-BGA | Intel (Altera)
EP20K200EBC652-1X ObsoleteAltera
EP20K1000EBC652-2X - 1M Gate APEX-20KE FPGA, 488 I/O, 652-BGA | Altera (Intel)
EP20K1000EBC652-2X NrndPagsanggunian na paghahambing
| Parametro | EP20K200EBC652-1X | EP20K1000EBC652-2X |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX 20KE | APEX-20KE |
| Series | APEX-20KE | — |
| Logic Elements / Cells | 8320 | — |
| Macros (Logic Cells) | 832 | — |
| Total RAM Bits | 106496 | — |
| Number of I/O | 376 | — |
| Core Voltage | 1.8 V (1.71 V to 1.89 V) | 1.8 V |
| Supply Voltage Range | 1.71 V to 1.89 V | — |
| Temperature na Operasyon | Industrial grade | 0 °C to +85 °C (commercial) |
| Speed Grade | -1X (fastest) | — |
| Packhaging | 652-BGA (45x45 mm) | 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch) |
| Supplier Device Package | 652-BGA | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.18 µm CMOS | 0.22 µm (some sources 0.15 µm) all-layer copper-metal CMOS |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status not in provided data] | Compliant |
| Katayuan ng Lifecycle | Obsolete / Discontinued | — |
| Device Logic Elements | — | 38,400 |
| Typical Gates | — | 1,000,000 system gates |
| Embedded Memory Bits | — | 327,680 bits |
| User I/O Pins | — | 488 |
| Maximum User I/O | — | 488 |
| Propagation Delay | — | 1.6 ns |
| Internal Maximum Frequency | — | 350 MHz |
| Logic Blocks / Macros | — | 2,560 macros |
| PLLs | — | 4 |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Altera configuration |