EP20K200EFC484-2X vs EP20K200EFC484-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200EFC484-2X sa pamamagitan ng Intel at EP20K200EFC484-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP20K200EFC484-1 EP20K200EFC484-1 - APEX 20KE FPGA 200K Gates 484-BGA | Altera

EP20K200EFC484-1 - APEX 20KE FPGA 200K Gates 484-BGA | Altera

EP20K200EFC484-1 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP20K200EFC484-2X EP20K200EFC484-1
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family APEX-20KE APEX 20KE
Logic Elements 8,320 —
LABs/CLBs 832 —
Total RAM Bits 106,496 —
Gate Count 200,000 —
User I/O Pins 376 —
Max Operating Frequency 205 MHz —
Core Supply Voltage (VCCINT) 1.71 V to 1.89 V (1.8 V nominal) —
I/O Supply Voltage (VCCIO) 3.3 V / 2.5 V (multi-standard) —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Packhaging 484-FBGA (23x23 mm) 484-BGA (FineLine BGA)
Package Code BGA, Ball, Square —
Propagation Delay 2.5 ns —
Temperature na Operasyon 0 °C to 85 °C -40 °C to +85 °C (industrial, inferred from grade code)
Speed Grade -2X —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance status]
Logic Elements / Cells — 8320
System Gates — 200000
Embedded Memory (Bits) — 106496
Maximum User I/O — 376
Number of PLLs — 4
Core Voltage — 1.8 V
Package Ball Count — 484
Uri ng Pagpapasok — Surface Mount
I/O Standard Support — LVDS, PCI, LVTTL, LVCMOS, SSTL, HSTL
Programming Interface — IEEE 1149.1 JTAG, passive serial, passive parallel
Level ng MSL — [DATA_NEEDED: MSL moisture sensitivity level]

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