EP20K200EFI484-2X vs EP20K200EFC484-1N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200EFI484-2X sa pamamagitan ng Intel at EP20K200EFC484-1N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K200EFI484-2X | EP20K200EFC484-1N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KE | APEX-20KE |
| Series | EP20K200E | — |
| System Gates | 200,000 | 200,000 |
| Logic Elements | 8,320 | 8,320 |
| Embedded RAM Bits | 106,496 | 106,496 |
| User I/O Pins | 376 | — |
| Maximum Frequency | 205 MHz | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Propagation Delay | 1.97 ns | 2.5 ns (per digchip reference) |
| Packhaging | 484-ball FineLine BGA | 484-ball FineLine BGA (23 mm × 23 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | -40 °C to +100 °C (TJ) | 0 °C to +85 °C (commercial) |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + Serial/Parallel PROM | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ (per APEX 20KE family datasheet) | — |
| Maximum User I/O | — | 376 |
| Core Voltage (VCCINT) | — | 1.8 V (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO range] |
| Maximum Internal Frequency | — | 367 MHz |
| Speed Grade | — | -1 |
| Programming Interface | — | IEEE 1149.1 JTAG |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |