EP20K200FC484-1XV vs EP20K200FC484-2X Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200FC484-1XV sa pamamagitan ng Altera at EP20K200FC484-2X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K200FC484-1XV EP20K200FC484-2X
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20K APEX 20K
Series APEX-20K® EP20K200
Device Type Field Programmable Gate Array (FPGA) FPGA (Field Programmable Gate Array)
Maximum System Gates 200,000 (typical) —
Maximum Logic Elements 8,320 8,320 cells
Maximum User I/O Pins 382 —
Embedded System Blocks (ESBs) 4 —
Total RAM Bits 106,496 —
Maximum Internal Frequency 250 MHz 200 MHz
Core Voltage (VCCINT) 1.71 V to 1.89 V —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Speed Grade -1 (with XV extended/reprocurement suffix) -2 (with LVDS support, "X" suffix)
Packhaging 484-FBGA (FC484), 23 mm x 23 mm, 1.27 mm pitch 484-pin FBGA (FineLine BGA), 1.0 mm pitch
Temperature na Operasyon Industrial / military (per variant) 0 °C to 85 °C (commercial)
Tindminan RoHS [DATA_NEEDED: exact RoHS statement] [DATA_NEEDED: RoHS compliance status]
Typical System Gates — 200,000
Embedded Memory (EAB) — 106,496 bits
Maximum User I/O — 382
Number of Logic Elements — 8,320
Propagation Delay — 3.0 ns
Core Supply Voltage — 2.5 V
Uri ng Pagpapasok — Surface Mount
Programmable I/O Standards — 1.8 V, 2.5 V, 3.3 V, LVTTL, LVCMOS, LVDS
JTAG Support — IEEE 1149.1 Boundary-Scan

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