EP20K200RC208-3 vs EP20K200RC208-1X Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200RC208-3 sa pamamagitan ng Intel at EP20K200RC208-1X sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K200RC208-3 EP20K200RC208-1X
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series APEX 20K —
Family APEX-20K® APEX-20KE
Logic Elements / Cells 8,320 —
Total System Gates 200,000 —
Embedded Memory (bits) 106,496 —
Number of I/O Pins 144 —
Packhaging 208-RQFP Exposed Pad (BFQFP) 208-pin PQFP / RQFP (28x28 mm), 0.5 mm pitch
Uri ng Pagpapasok Surface Mount Surface Mount (gull-wing leads)
Process Technology 0.22 µm CMOS 0.18 µm CMOS
Core Voltage 1.8 V 1.8 V (±5%)
I/O Standard LVDS (3.3 V / 2.5 V) —
Maximum Operating Frequency 167 MHz —
PLLs 4 —
Speed Grade -3 -1X (1.8 V core, PQFP-208 pinout)
Temperature na Operasyon -40°C to +85°C (Industrial) 0 °C to +85 °C (commercial)
Programming Interface IEEE 1149.1 JTAG —
In-System Programmable Yes —
Hot Socketing Yes —
Tindminan RoHS Compliant Compliant (lead-free PQFP package)
Logic Elements — 8,320 cells
Typical Gate Count — 200,000 gates
Embedded RAM Bits — 106,496 bits
Embedded RAM Blocks (ESBs) — 4 lanes / 52 ESBs
Maximum User I/O Pins — 144 (PQFP-208 variant)
I/O Standards Supported — LVTTL, LVCMOS, PCI, SSTL-2/3, LVDS, GTL+
Configuration Interface — IEEE 1149.1 JTAG, serial, passive parallel (PPA), EPC configuration devices
MultiCore Architecture — LUT logic + product-term logic + embedded memory
PLL Count — 4 enhanced PLLs (with programmable phase shift)
Moisture Sensitivity Level — MSL 3 (per JEDEC J-STD-020, applicable to PQFP)

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