EP20K200RC208-3 vs EP20K200RC208-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200RC208-3 sa pamamagitan ng Intel at EP20K200RC208-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K200RC208-3 | EP20K200RC208-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | APEX 20K | APEX-20K |
| Family | APEX-20K® | APEX-20K MultiCore FPGA |
| Logic Elements / Cells | 8,320 | — |
| Total System Gates | 200,000 | — |
| Embedded Memory (bits) | 106,496 | 106,496 |
| Number of I/O Pins | 144 | — |
| Packhaging | 208-RQFP Exposed Pad (BFQFP) | 208-BQFP / 208-RQFP with Exposed Pad |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | 0.22 µm CMOS | [DATA_NEEDED: process node] |
| Core Voltage | 1.8 V | — |
| I/O Standard | LVDS (3.3 V / 2.5 V) | — |
| Maximum Operating Frequency | 167 MHz | — |
| PLLs | 4 | — |
| Speed Grade | -3 | -2 (mid-speed, industrial) |
| Temperature na Operasyon | -40°C to +85°C (Industrial) | -40C to +85C (industrial) |
| Programming Interface | IEEE 1149.1 JTAG | — |
| In-System Programmable | Yes | — |
| Hot Socketing | Yes | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance] |
| Logic Elements (LEs) | — | 8320 |
| System Gates | — | 200,000 (typical) |
| Maximum User I/O | — | 144 |
| Bilang ng Pin | — | 208 |
| Supply Voltage (Core) | — | [DATA_NEEDED: core VCC] |
| Supply Voltage (I/O) | — | 3.3 V (multi-standard I/O) |
| Configuration Interface | — | JTAG (IEEE 1149.1) + Altera legacy scheme |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |