EP20K400BC652-1V vs EP20K400GC652-1XV Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400BC652-1V sa pamamagitan ng Altera at EP20K400GC652-1XV sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400BC652-1V | EP20K400GC652-1XV |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20KC | — |
| Family | APEX 20K | APEX 20K |
| Device Sub-Family | EP20K400 | — |
| System Gates | 1,052,000 | — |
| Maximum Logic Elements | 212,992 | — |
| Macrocells / LABs | 16640 | — |
| Embedded Memory (bits) | 212,992 | — |
| Maximum User I/O | 502 | 502 |
| Speed Grade | -1 | -1 (standard) |
| Clock-to-Output (Tco) | 2.5 ns | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 2.5 V | — |
| Packhaging | 652-BGA (FineLine, 45 x 45 mm) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (commercial) | 0 C to +85 C |
| Configuration | SRAM-based, JTAG IEEE 1149.1 | — |
| Architecture | MultiCore (LUT + product-term + ESB) | MultiCore (LUT + EAB + FastTrack interconnect) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Compliant (lead-free, V suffix) |
| Logic Elements (Macros) | — | 1664 |
| Typical System Gates | — | 400,000 |
| Embedded SRAM | — | 212,992 bits |
| Core Supply Voltage | — | 2.5 V |
| Propagation Delay | — | 2.5 ns |
| Logic Family | — | CMOS |
| Package Type | — | BGA-652 (thermally enhanced) |
| Programming Interface | — | JTAG (IEEE 1149.1) / passive serial |