EP20K400CB652C8N vs EP20K400CB652C9N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CB652C8N sa pamamagitan ng Intel at EP20K400CB652C9N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CB652C8N | EP20K400CB652C9N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX 20KC | APEX 20KC |
| Device Logic Elements | 16640 | — |
| System Gates | 400000 | 400,000 |
| Process Technology | 0.15 um CMOS, all-layer copper | — |
| Core Supply Voltage | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Supply Voltage | 2.5 V | — |
| User I/Os | 502 | — |
| Programmable I/O Lines | 488 | — |
| Inputs | 484 | — |
| Outputs | 480 | — |
| Propagation Delay | 2.5 ns | 2.0 ns |
| Internal Operating Frequency | 301.21 MHz | — |
| Packhaging | BGA-652 | BGA-652 (Plastic Ball Grid Array, 652 balls) |
| Logic Family | CMOS | CMOS |
| Temperature na Operasyon | 0 C to +85 C | — |
| PCI Support | PCI Local Bus 2.2, 33/66 MHz, 32/64-bit | — |
| Memory Support | DDR SDRAM, ZBT SRAM | — |
| Architecture | MultiCore (LUT + embedded system blocks) | MultiCore (LUT logic + Embedded System Blocks) |
| Tindminan RoHS | unknown | Unknown (legacy Altera part - verify with distributor) |
| Series | — | EP20K400 |
| Device Type | — | Programmable Logic Device (SOPC FPGA) |
| Logic Elements | — | 16,640 |
| Maximum User I/Os | — | 502 |
| Total Memory Bits | — | 212,992 (per chip) |
| Maximum Internal Frequency | — | 250 MHz |
| Core Process Technology | — | 0.15 µm all-layer copper CMOS |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V |
| Hanay ng Temperature na Operasyon | — | 0 °C to +85 °C (Commercial) |
| Uri ng Pagpapasok | — | Surface Mount |
| Configuration Interface | — | IEEE 1149.1 JTAG, serial passive parallel async |