EP20K400CB652C9ES vs EP20K400CB652I9 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CB652C9ES sa pamamagitan ng Intel at EP20K400CB652I9 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CB652C9ES | EP20K400CB652I9 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Series | APEX 20KC | — |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements / Cells | 16640 | — |
| Total System Gates | 400000 | — |
| Embedded Memory (Bits) | 212992 | — |
| Number of User I/O | 488 | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Number of Logic Array Blocks | 1040 | — |
| Maximum Operating Frequency | 250 MHz | — |
| Core Voltage | 1.8 V | 1.8 V |
| Process Technology | 0.15 µm CMOS | 0.15 um CMOS |
| Hanay ng Temperature na Operasyon | 0°C to +85°C (Commercial) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Packhaging / Kaso | 652-BGA | — |
| Level ng MSL | 3 (168 Hours) | — |
| Packaging | Tray | — |
| Programmability Type | In-system programmable (SRAM-based) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL | — |
| JTAG (IEEE 1149.1) | Yes | — |
| PLL | Yes (4-phase) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance verification] |
| Logic Elements | — | 16,640 cells |
| System Gates | — | 400,000 |
| Maximum User I/O | — | 488 |
| Embedded Memory Bits | — | 212,992 bits |
| Embedded System Blocks (ESBs) | — | 104 |
| Maximum Frequency | — | 250 MHz |
| Packhaging | — | 652-pin LBGA (CB) |
| Maximum Seated Height | — | 1.63 mm |
| Temperature na Operasyon | — | -40C to +85C (industrial, 'I' grade) |
| Speed Grade | — | -9 |
| Total Terminals | — | 652 |