EP20K400EFC672-1 vs EP20K400FI672-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400EFC672-1 sa pamamagitan ng Intel at EP20K400FI672-1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400EFC672-1 | EP20K400FI672-1 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KE | — |
| System Gates | 400,000 | — |
| Logic Elements / Cells | 16,640 | — |
| Maximum User I/O | 488 | — |
| Embedded Memory | 212,992 bits | — |
| Core Voltage | 1.8 V | — |
| I/O Voltage Tolerance | 2.5 V / 3.3 V compatible | — |
| Technology | 0.22 um CMOS | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Internal Operating Frequency | 368 MHz | — |
| Speed Grade | -1 | -1 |
| Packhaging | 672-FBGA (FineLine BGA) | 672-ball PBGA (FineLine BGA, 1.0 mm pitch) |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | 0C to +85C (Commercial) | Industrial (per 'I' suffix) |
| Logic Family | CMOS | — |
| Architecture | MultiCore (LUT + EAB + product-term) | — |
| Series | — | APEX 20K |
| Device Family | — | APEX-20K Field Programmable Gate Array |
| Typical Gates | — | 400,000 |
| Logic Elements | — | 212,992 |
| Logic Array Blocks (LABs) | — | 16,640 |
| User I/O Pins | — | 502 |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 672 |
| Package Code (JEDEC) | — | S-PBGA-B672 |
| Core Supply Voltage (VCCINT) | — | 2.5 V nominal (2.375 V to 2.625 V) |
| Process Technology | — | CMOS |
| Level ng MSL | — | 3 |
| Peak Reflow Temperature | — | 220 C |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |