EP20K400FC672-3 vs EP20K400FC672-4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FC672-3 sa pamamagitan ng Altera at EP20K400FC672-4 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400FC672-3 | EP20K400FC672-4 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX 20K | APEX 20K |
| Device Logic Elements | 16,640 cells | 16640 |
| Typical Gate Count | 400,000 system gates | — |
| Maximum User I/Os | 502 | — |
| Propagation Delay | 2.5 ns | — |
| Internal Performance | 167 MHz | — |
| Process Technology | 0.22 µm CMOS | MultiCore (LUT + ESB) |
| Core Supply Voltage | 2.5 V | — |
| Logic Family | CMOS, SRAM-based | — |
| Packhaging | 672-pin FC-FBGA | 672-BBGA (FC) |
| Package Code | BGA | — |
| Number of Terminals | 672 | — |
| Terminal Form | Ball (BGA) | — |
| Speed Grade | -3 (commercial fastest) | -4 (slowest) |
| Temperature na Operasyon | 0 °C to 85 °C | [DATA_NEEDED: commercial/industrial temp range] |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming Method | SRAM, JTAG (ByteBlaster) | — |
| Katayuan ng Lifecycle | Obsolete / Legacy | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Typical Gates | — | 400000 |
| System Gates | — | 212992 |
| Embedded Memory (Kbits) | — | 502 |
| Maximum User I/O | — | [DATA_NEEDED: user IO count] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 C |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCCINT/VCCIO] |
| REACH Status | — | unknown |
| Lead-Free | — | unknown |
| Design Tool | — | Quartus II (legacy) |