EP20K400FC672-4 vs EP20K400FC672-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FC672-4 sa pamamagitan ng Intel at EP20K400FC672-3 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400FC672-4 | EP20K400FC672-3 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | APEX 20K | APEX 20K |
| Device Logic Elements | 16640 | 16,640 cells |
| Typical Gates | 400000 | — |
| System Gates | 212992 | — |
| Embedded Memory (Kbits) | 502 | — |
| Maximum User I/O | [DATA_NEEDED: user IO count] | — |
| Speed Grade | -4 (slowest) | -3 (commercial fastest) |
| Packhaging | 672-BBGA (FC) | 672-pin FC-FBGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 | — |
| Peak Reflow Temperature | 220 C | — |
| Temperature na Operasyon | [DATA_NEEDED: commercial/industrial temp range] | 0 °C to 85 °C |
| Volte ng Pagbibigay | [DATA_NEEDED: VCCINT/VCCIO] | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| Lead-Free | unknown | — |
| Process Technology | MultiCore (LUT + ESB) | 0.22 µm CMOS |
| Design Tool | Quartus II (legacy) | — |
| Typical Gate Count | — | 400,000 system gates |
| Maximum User I/Os | — | 502 |
| Propagation Delay | — | 2.5 ns |
| Internal Performance | — | 167 MHz |
| Core Supply Voltage | — | 2.5 V |
| Logic Family | — | CMOS, SRAM-based |
| Package Code | — | BGA |
| Number of Terminals | — | 672 |
| Terminal Form | — | Ball (BGA) |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Programming Method | — | SRAM, JTAG (ByteBlaster) |
| Katayuan ng Lifecycle | — | Obsolete / Legacy |