EP20K400FI672-2N vs EP20K400FI672-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-2N sa pamamagitan ng Altera at EP20K400FI672-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoletePagsanggunian na paghahambing
| Parametro | EP20K400FI672-2N | EP20K400FI672-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | APEX 20K | APEX-20K |
| Typical Gates | 400,000 | — |
| Logic Elements / Cells | 16,640 | — |
| Maximum User I/O | 488 | — |
| Embedded Memory Bits | 212,992 bits | 212992 |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count per family datasheet] | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Voltage | 2.5 V | — |
| Maximum Frequency | 200 MHz | — |
| Packhaging | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) | — |
| Package Body Size | 27 x 27 mm | — |
| Terminal Pitch | 1.0 mm | — |
| Propagation Delay | 3.1 ns | 2.5 ns |
| Speed Grade | -2 | — |
| Temperature na Operasyon | Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] | 0 °C to +85 °C (Commercial) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 | — |
| Peak Reflow Temperature | 220 °C | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Tindminan RoHS | Compliant (lead-free) | Lead-free / RoHS Compliant |
| Configuration Modes | PS, PPS, PPA, JTAG | JTAG, Passive Serial, Passive Parallel |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, HSTL | — |
| Logic Elements | — | 16640 |
| Maximum Gates | — | 400,000 gates |
| User I/Os | — | 502 |
| Number of Macros | — | 1664 |
| Core Supply Voltage | — | 2.5 V |
| Maximum Internal Frequency | — | 200 MHz |
| Package Type | — | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) |
| PLLs (Phase-Locked Loops) | — | 4 |